Digital display devices are becoming increasingly popular, such as LCD display units, plasma display units, digital light projection units and any other digital display devices. Such display devices that employ format converting attempt to convert the format that arrive from image sources—such as personal computers, game boxes, DVD players, MPEG decoders, or other sources—to the display image format. Signals that arrive from personal computers for example may be communicated with timing modes (such as VESA type timing modes) that may be transmitted with relatively loose timing accuracy compared to those used for video applications. The timing signals, such as horizontal synchronization signals and vertical synchronization signals or other suitable display timing signals may vary as much as plus or minus 0.25% out of specification. Such incoming timing signals can be sources of jitter and may be not be desirable for high quality video clocking purposes.
Several known format converting circuits are known which are typically co-located with the digital display unit and include a digital pixel clock generation circuit that may be, for example, within the housing containing the digital display panel. One example of a known digital pixel clock generation circuit for a display may convert incoming display signals, such as horizontal synchronization signals directly into a clock for driving the digital display. The clock is often referred to as a pixel output clock. Such clock generation circuits may use an external phase locked loop circuit designed to handle a low reference clock signal. However, the external phase locked loop (PLL) circuit is typically in the form of a chip or other suitable integrated circuit and can be expensive. The incoming horizontal synchronization's poor jitter characteristics may also be reflected in the local output pixel clock as its jitter characteristics may be partially passed along by the PLL circuit. In addition, it is not always possible to convert the external incoming pixel clock from the image source into a suitable frequency when performing format conversion.
Other solutions may have an output pixel clock that does not lock to an incoming pixel clock from an image source, but instead may run use an independently derived and unlocked clock. These solutions will drop or repeat pictures to prevent an internal picture buffer from eventually overflowing of underflowing. Dropping or repeating pictures can be unacceptable when the displays are used for video or animated games.
As a result, other prior art digital pixel clock generation circuits have been developed. FIG. 1 illustrates a functional block diagram of one example of a digital display control circuit that employs a digital pixel clock generation circuit 10. The circuit includes, for example, a multiplexer 11 which outputs one of a selected input source and corresponding input pixel clock or timing information for use by the display control circuit. The digital display control circuit performs format conversion as needed by the digital display. The digital pixel clock generation circuit 10, as known in the art, employs an independent clock source other than the input pixel clock received from the image source. In this example, the independent clock source 12 is a voltage controlled crystal oscillator. Known digital pixel clock generation circuits 10 may receive, for example, image data and corresponding presentation time information 14 from a suitable image source such as a cable set top box, a DVD player, personal computer, game box or other suitable image source, along with an input pixel clock 16 which may be provided, for example, by the image source.
The digital pixel clock generation circuit 10 is typically part of other digital display circuitry that is co-located with the digital display to provide scaling and other display specific encoding. For example, as shown, an image scaler 18 that is coupled to a frame buffer 20 may be employed as well as a display encoder 22 which is provides timing information from a CRTC 32 and image data 24 to the digital display 26. “CRTC” stands for “Cathode Ray Tube Controller”; however, it is a term now used to represent a block that generates timing signals useful for driving display devices in general—including newer devices that do not use CRT technology. The digital pixel clock generation circuit 10 includes a control circuit 28 and a PLL 30. The control circuit 28 receives actual image presentation time data 36, from the CRTC 32 and compares it with incoming presentation time information 14 from the image source to determine any difference between them. The control circuit 28 then provides a suitable timing adjustment control signal 40 to, in one embodiment, the PLL 30 to speed up or reduce the pixel output clock 42 from the PLL. The independent clock source 12 feeds the PLL 30 with an independent clock signal 44, which the PLL then converts to a pixel output clock, 42, based on a ratio that is adjusted by input 40 to the PLL. PLLs can convert one clock to another. Typically they have a wide conversion range but limited stepping granularity. The granularity is often overly coarse for the application of converting one kind of video signal into another. This will result in a pixel clock that is never quite the required frequency, but instead hopping back and forth between two or more nearby frequencies. The hopping back and forth introduces jitter in the output clock which can reduce the video quality of the digital display device 26. Some PLL designs endeavor to overcome the granularity limitations of a PLL by rapidly changing one of the PLL's control parameters but such techniques also introduce undesirable jitter into the output clock.
Another technique used is to control the frequency of the reference clock 12 directly. This can be done if the reference clock is a Voltage Controlled Crystal Oscillator, for example. In this case, the PLL can stay fixed at one conversion ratio and thus not be a source of jitter. The VCXO is adjusted by converting control signal 40 into a voltage which will be used to speed up or slow down the VCXO. This approach is limited because the VCXO, while it has good stepping granularity, has poor range. There are a wide variety of format conversion problems which can not be handled with the VCXO's limited range. Also, the VCXO is a significantly more expensive clock reference than a standard crystal oscillator.
A combination of both solutions may appear to overcome the limited stepping granularity of one and the limited range of the other; however, you can't get the range without stepping and introducing a VCXO will not eliminate the jitter introduced by the act of stepping a PLL.
Accordingly, a need exists for a circuit and method that overcomes one or more of the above problems.